Latency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC

          @misc{ scivideos_oai:cds.cern.ch:3025787,
            doi = {},
            url = {https://videos.cern.ch/record/3025787},
            author = {},
            keywords = {},
            language = {en},
            title = {Latency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC},
            publisher = {},
            year = {2026},
            month = {may},
            note = {oai:cds.cern.ch:3025787 see, \url{https://scivideos.org/cern-cds/3025787}}
          }
          

Abstract

Real-time control algorithms for power converters in particle accelerators require flexible platforms capable of high iteration rates (up to 100 kHz). This work evaluates the suitability of the Zynq UltraScale+ SoC (A53 cores) for such applications. After characterizing the access time of the most basic FPGA-CPU access path, we show how this path is unsuitable for real time controls. We then propose an alternative system, characterizing the critical metrics: PL access, Memory access, ACP latency performance, and Interrupt latency. We identify a suitable data path for real time controls and propose an exploitation paradigm for achieving reliable sub-microsecond latency.

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