Recovered Clock Phase Monitoring on AMD Transceivers for Deterministic Timing

          @misc{ scivideos_oai:cds.cern.ch:3025786,
            doi = {},
            url = {https://videos.cern.ch/record/3025786},
            author = {},
            keywords = {},
            language = {en},
            title = {Recovered Clock Phase Monitoring on AMD Transceivers for Deterministic Timing},
            publisher = {},
            year = {2026},
            month = {may},
            note = {oai:cds.cern.ch:3025786 see, \url{https://scivideos.org/cern-cds/3025786}}
          }
          

Abstract

After the Phase-II upgrade of the Large Hadron Collider at CERN, pile-up discrimination in the CMS Electromagnetic Barrel Calorimeter demands a clock system with picosecond precision and deterministic phase. Although modern electronics can achieve sub-5 ps RMS jitter, widely used FPGAs do not ensure phase repeatability after reset. Their Multi-Gigabit Transceivers prioritize bit error rate robustness over deterministic recovered clock phase. Measurements with the Barrel Calorimeter Processor (BCP-V2) show that MGT resets can yield two discrete recovered clock phases about 10 ps apart, while the internal Delay Aligner adds temperature-dependent drift. The BCP-V2 integrates a picosecond-resolution monitor achitecture that extracts the clock before the Delay Aligner and the FPGA fabric (RXRECCLKOUT) and compares it to RXUSRCLK, typically used as the LHC reference, using a Digital Dual Mixer Time Difference method, enabling real-time detection of clock phase jumps and drifts.

00:00:00 Slide 1
00:00:25 Slide 2
00:00:52 Slide 3
00:02:21 Slide 4
00:02:37 Slide 5
00:02:53 Slide 6
00:03:39 Slide 7
00:04:42 Slide 8
00:05:04 Slide 9
00:05:31 Slide 10
00:06:01 Slide 11
00:06:51 Slide 12
00:07:18 Slide 13
00:07:49 Slide 14
00:08:20 Slide 15
00:09:05 Slide 16
00:09:37 Slide 17
00:10:41 Slide 18
00:12:01 Slide 19
00:14:44 Slide 20
00:15:59 Slide 21
00:16:55 Slide 22
00:19:06 Slide 23