SystemVerilog Hacks: Circumventing the Limitations of SystemVerilog

          @misc{ scivideos_oai:cds.cern.ch:3025785,
            doi = {},
            url = {https://videos.cern.ch/record/3025785},
            author = {},
            keywords = {},
            language = {en},
            title = {SystemVerilog Hacks: Circumventing the Limitations of SystemVerilog},
            publisher = {},
            year = {2026},
            month = {may},
            note = {oai:cds.cern.ch:3025785 see, \url{https://scivideos.org/cern-cds/3025785}}
          }
          

Abstract

SystemVerilog is a powerful language with relatively good compiler support. However, some inexplicable oversights and limitations in the SystemVerilog standard can cause HDL designers to expend significant work that would have been unnecessary had simple tweaks in the language's standard been adopted. For example, one limitation of SystemVerilog is that a "struct" cannot be parameterized more than once, i.e. the same "struct" code needs to be rewritten every time any of the parameters that define it change. A similar issue affects SystemVerilog functions. With regards to SystemVerilog interfaces, a necessary but lacking feature of SystemVerilog would be the ability to propagate parameters directly from an interface to other parts of the code, without needing to pass the parameters themselves up and down the design hierarchy. In this presentation we discuss these and other issues and their workaround solutions that enable the designer to make much more efficient use of SystemVerilog.

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