CDCs, FIFOs, and Width Converters: How to Combine Open Logic Building Blocks Correctly

          @misc{ scivideos_oai:cds.cern.ch:3025784,
            doi = {},
            url = {https://videos.cern.ch/record/3025784},
            author = {},
            keywords = {},
            language = {en},
            title = {CDCs, FIFOs, and Width Converters: How to Combine Open Logic Building Blocks Correctly},
            publisher = {},
            year = {2026},
            month = {may},
            note = {oai:cds.cern.ch:3025784 see, \url{https://scivideos.org/cern-cds/3025784}}
          }
          

Abstract

In FPGA design, correctly handling clock domain crossings, buffering data streams, and matching data widths is critical for reliable and maintainable systems. The Open Logic FPGA Standard Library (open source) provides building blocks for these challenges, but many users struggle to understand when and how to combine them effectively. This talk will walk you through the CDCs, FIFOs, and width converters in Open Logic and provide clear guidance on selecting and composing them for different scenarios, including asymmetric buffering and varying bandwidth requirements. Attendees will leave with actionable rules and patterns to use Open Logic building blocks correctly, avoid common pitfalls, and simplify FPGA system design.

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